Integrated circuits (ICs) are semiconductor devices that contain active devices such as transistors and diodes and/or passive devices such as capacitors, resistors and inductors. Performance characteristics of the ICs are typically improved by reducing the dimensions of the active and/or passive devices in the IC. The reduced dimensions of the IC devices allow an increased number of devices to be fabricated in the same chip area to provide additional functionality and/or the same number of devices can be fabricated in a reduced chip area. The reduced dimensions also typically reduce I2R losses and increase switching speeds. One restraint on further size reductions relates to layout requirements of data input/output or power/ground connections that are made to the IC.
Typically, the IC is mounted on a package. Solder bumps and bond wires on the package are connected to bond pads on the IC. Pins provide external connections to the package. The bond pads are typically made of aluminum (Al) and/or aluminum alloy (Al-alloy). The bond pads are deposited onto the IC using conventional sputtering and photolithography techniques. The conventional process for forming bond pads is both expensive and complex.
The bond pads formed on the IC are typically located in a first region of the IC. The bond pads provide connections to metal interconnects and vias, which in turn provide connections to active and/or passive devices of the IC. The bond pads are usually not formed over a second region that contains the active and/or passive devices. For example, the first region may include an outer perimeter of the IC that surrounds the second or inner region of the IC.
One reason for the mutually exclusive first and second regions is related to thermal and/or mechanical stress that occurs during wire bonding. An outermost metal interconnection layer is typically covered by a passivation layer. Openings in the passivation layer expose contact pads, which are patterned in the outermost metal interconnect layer. Wires are bonded to the contact pads. If active regions are located below the contact pads, the processing will damage the underlying dielectric, the active devices and/or the passive devices. The dielectric is particularly susceptible if it is formed using a weak or low-k dielectric metal.
Referring now to FIG. 1a, conventional bond pads 10-1, 10-2, . . . , 10-n (collectively identified by 10) are typically arranged in a first region 12 of an integrated circuit (IC) die 14. The first region 12 may correspond to an outer region or perimeter of the IC 14, although other arrangements may be used. The bond pads 10 are laterally displaced from a second region 18, which is separate from the first region 12. The second region 18 contains underlying dielectric layers, active devices, and/or passive devices of the IC die 14. The second region 18 may be a central region that is surrounded by the outer region. Positioning the dielectric layer(s), the active device(s) and/or the passive device(s) in laterally separate regions avoids damage that may be caused by thermal and/or mechanical stress that occurs during wire bonding.
Referring now to FIG. 1b, an exemplary active device 30 is located in the second region 18 and includes a transistor 32 with a gate 34, a source 36, a drain 38, and field isolation regions 40. While the transistor 32 is shown for illustration purposes, other types of active and/or passive devices may be located in the second region 18. One or more dielectric layers 44-1 and 44-2 and one or more metal interconnect layers 48-1, 48-2, . . . , and 48-p (collectively identified as 48) and vias (not shown) are used to provide connections between the active and/or passive devices and contact pads 49, which are formed in the outermost metal interconnect layer 48. Vias are typically used to provide connections between the metal interconnect layers.
A passivation layer 58 is typically formed on top of the outermost metal interconnect layer. Openings 54 in the passivation layer expose the contact pads 49. Wire 50 is bonded to the contact pad through passivation opening 54. While only one active device and one bond pad is shown, additional active devices, passive devices and/or bond pads can be provided. The passivation layer is typically deposited using chemical vapor deposition (CVD), although other processes may be used. The metal interconnect layers and vias are typically made of Al or Al-alloy, although other materials may be used.
The conventional layout depicted in FIGS. 1a and 1b requires lateral separation between the first region 12 containing the bond pad(s) and the second region 18 containing the underlying dielectric layer(s), active device(s) and/or passive device(s). This requirement significantly increases the size of the IC die 14 because the second region 18 is not available for bond pads.